View L8150_1118862.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

march 2006 rev 1 1/37 1 L8150 brushless motor predriver feature integrated predriver ic for 3 phase bl motor. integrated smooth driving concept with sinusoidal driving waveforms. bcd5 technology 0.6mm. package: so28. three hall effects, differential input comparators. integrated undervoltage lockout (vcc). pwm output duty (voltage) control / torque optimizer / protection functions pwm carrier 17khz min / integrated dead time functions c-mos level predriver output (high active) free run function dead time (3 values selectable) sinusoidal waveform pwm logic detected rotation speed (fg) output terminal pwm duty control by analog input (kval control) forward/backward rotation input terminal (fr) / rotation direction detection output terminal (dm) thermistor connection terminal (thermal protection) torque optimizer terminal controlled by analog voltage input v regulator output terminalexternal hvic bootstrap capacitor pre-charge function external hvic bootstrap capacitor refresh function during 120 degree drive (rectangular drive). this means both upper and lower chopping and low side current recirculation for rectangular drive. current limiter circuit vcc lower voltage protection / vdc over voltage protection circuit / hall sensor fail protection fault signal output description the L8150 device is a motor predriver intended to drive brushless fan motors with hall effect sensors. the device, realized in bcd5 0.6mm mixed technology, is characterized by a mostly digital architecture assuring high integration density and high test coverage. the L8150 with few external components forms a complete control circuit, since the smooth driver logic is fully integrated: its peculiar driving solution (smooth driving) allows a very low current ripple and speed control even at low rotation speeds. order codes so28 part number temp range, cpackage packing e-L8150 -20 to 95 so28 tube e-L8150tr -20 to 95 so28 tape & reel www.st.com
contents L8150 2/37 contents 1 block diagram & pins description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.2 pins description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.2 operating condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3 electrical characteristcs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.1 drive stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.2 output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.3 i/o . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.4 hall sensor input terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.5 protection functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.6 pwm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.7 system clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.8 external hvic bootstrap capacitor initialization . . . . . . . . . . . . . . . . . . . 14 4.9 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.10 others . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5 operating description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.1 free-run (fs) and reset (sd) functions . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.2 smooth drive and control logic description . . . . . . . . . . . . . . . . . . . . . . . 16 5.3 speed control circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 6 precharge and hall effects filtering time description . . . . . . . . . . . . . . 24 6.1 startup sequence with fs signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 6.2 startup sequence with sd signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 7 application example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
L8150 contents 3/37 8 input output pins interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 9 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 10 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
list of tables L8150 4/37 list of tables table 1. pins description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 table 2. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 table 3. operating condition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 table 4. supply voltage terminal vcc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 5. regulator output terminal vreg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 6. driver output terminal uh,vh,wh,ul,vl,wl . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 7. dead time select terminal sd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 8. hall sensor input terminal hup,hun,hvp,hvn,hwp,hwn . . . . . . . . . . . . . . . . . . . . . . . 9 table 9. torque optimizer input terminal t.o. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 10. over current sense input terminal r . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 11. forward backward select terminal fr (note 7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 12. thermal sense input terminal tsd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 13. fg output terminal fg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 14. osc terminal osc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 15. op amp input output terminal intin+, intin-, intout (note 3, note 4). . . . . . . . . . . . . . . 10 table 16. over voltage protection terminal ov . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 17. low voltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 18. faults output terminal faults . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 19. rotation direction detection terminal dm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 20. kval contro . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 21. phase shift . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 22. 7 different values of the signal pos . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 23. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
L8150 list of figures 5/37 list of figures figure 1. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 2. pins connection (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 3. kval control by vsp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 4. external circuit for vsp control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 5. 16 bit counter operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 6. smooth drive pattern (forward) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 7. phase shift vs input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 8. smooth drive pattern (reverse). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 9. rectangular drive pattern (forward) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 10. rectangular drive pattern (reverse) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 11. filtering circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 12. filter block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 13. duty cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 14. startup sequence forced by fs comparator, assuming the motor is not rotating . . . . . . . . 24 figure 15. startup sequence forced by fs co mparator, supposing the motor rotating quickly in the direction imposed by the fr signal: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 16. startup sequence forced by fs co mparator, supposing the motor rotating quickly in the direction opposite to that imposed by the fr signal . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 17. startup sequence forced by fs comparat or, supposing the motor rotating too quickly . . . 27 figure 18. startup sequence forced by sd, supposing the motor stopped . . . . . . . . . . . . . . . . . . . . . 28 figure 19. startup sequence forced by sd , supposing the motor rotating quickly in the direction imposed by the fr signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 20. startup sequence forced by sd , supposing the motor rotating quickly in the direction not imposed by the fr signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 21. startup sequence forced by sd signal, supp osing the motor rotating too quickly . . . . . . . 30 figure 22. basic motor control circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 23. 3 phases motor control circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 24. pins: tsd, ov, sdt, intinn, intinp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 3 figure 25. pins: to . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 26. pins: rf . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 27. pins: intout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 28. pins: osc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 29. pins: fg, dm, fault . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 30. esd clamping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 31. recirculation diode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 32. pins: fr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 33. pins: hwn, hwp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 34. pins: hun, huvp, hvn, hvp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 35. pins: uh, ul, vh, vl, wh, wl . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 36. so-28 mechanical data & package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
block diagram & pins description L8150 6/37 1 block diagram & pins description 1.1 block diagram figure 1. block diagram 1.2 pins description figure 2. pins connection (top view) rf wh wl vh vl ul uh sdt hup osc fault intinp intout intinn to vreg vcc gnd 1 3 2 4 5 6 7 8 9 26 25 24 23 22 20 21 19 27 10 28 uhn fr d01in1259 hvp hvn hwp dm ov tsd 11 12 13 18 16 17 15 14 hwn fg
L8150 block diagram & pins description 7/37 table 1. pins description n pin function 1 rf external sense resistance pin 2 wh w bridge high-side mos output command 3 wl w bridge low-side mos output command 4 vh v bridge high-side mos output command 5 vl v bridge low-side mos output command 6 uh u bridge high-side mos output command 7 ul u bridge low-side mos output command 8 sdt dead time selection input pin 9 hup hall sensor differential input 10 hun hall sensor differential input 11 hvp hall sensor differential input 12 hvn hall sensor differential input 13 hwp hall sensor differential input 14 hwn hall sensor differential input 15 fg multiplexed hall effects output 16 dm motor direction detected output 17 ov over-voltage comparator input 18 tsd external thermal shutdown input 19 fr forward/backward rotation input 20 osc external 20.5k ? polarization resistance pin 21 fault fault signal output 22 intinp error amplifier reference input pin 23 intinn error amplifier negative input pin 24 intout error amplifier output 25 to torque optimizer analog input 26 vreg internal 5v regulator output 27 vcc external 15v supply 28 gnd ground pin
electrical specifications L8150 8/37 2 electrical specifications 2.1 absolute maximum ratings 2.2 operating condition table 2. absolute maximum ratings no. item symbol terminal value unit remark 1 vcc supply voltage v cc vcc 20 v 2 fg terminal voltage v fg fg -0.3/20 v 3 fault terminal voltage v fault fault -0.3/20 v 4 dm terminal voltage v dm dm -0.3/20 v 5 fg, fault, dm currents i od fg, fault, dm 15 ma maximum current 6rf voltage v rf rf -5 to vreg v 7 other pin voltage sdt,hup,hun,hvp hvn,hwp,hwn,ov,tsd fr,intinn,intinp,to -0.3 / 6 v 8 inject current sdt,hup,hun,hvp hvn,hwp,hwn,ov,tsd fr,intinn,intinp,to 5ma 9 operating ambient temp. t opg -20/+95 c 10 junction temp. t j 150 c 11 storage temp. t stg -55/+150 c 12 latch up tolerance all pin 200 ma 13 esd tolerance all pin 200 v machine model 2000 v human body model table 3. operating condition no. item symbol terminal min type max unit remark 1 supply voltage v cc vcc 12.75 15 17.25 v
L8150 electrical characteristcs 9/37 3 electrical characteristcs t amb = 25 c, v cc =15v, v reg = 5v unless otherwise specified t table 4. supply voltage terminal vcc no. item symbol terminal min typ max unit remark 1 current consumption 1-1 i cc1-1 vcc 10.0 20.0 ma table 5. regulator output terminal vreg no. item symbol terminal min typ max unit remark 1 output voltage v reg vreg 4.7 5.0 5.3 v 2 voltage variation ? v reg1 vreg 40 100 mv vcc1=12.75 to 17.25v 3 load variation ? v reg2 vreg 5 30 mv io=5 to 20ma (note 1) 4 thermal coefficient ? v reg3 vreg 0 mv/ c table 6. driver output terminal uh,vh,wh,ul,vl,wl no. item symbol terminal min typ max unit remark 2 h level output voltage 2 v oh uh,? 3.70 v ioh=-2.5ma 4 l level output voltage 2 v ol uh,? 0.40 v iol=2.5ma table 7. dead time select terminal sd no. item symbol terminal min typ max unit remark 1 h level input voltage v sdth sdt 9/10 vreg vreg v dead time =0 usec 2 m level input voltage v sdtm sdt 4/10 vreg 6/10 vreg v dead time=1.5usec (t deadtime= 15xt ck) 3 l level input voltage v sdtl sdt 0 1/10 vreg v dead time=1.0usec (t deadtime= 10xt ck) table 8. hall sensor input te rminal hup,hun,hvp,hvn,hwp,hwn no. item symbol terminal min typ max unit remark 1 input bias current i hb(ha) hup,? -2 ua 2 common mode input range v icm hup,? 0.50 3.00 v for hall device 3 input voltage range v i hup,? 0.00 5.00 v for hall ic, note 2 4 hall input sensitivity hup,? 50 mvp-p 5 hysteresis width ? v in(ha) hup,? 20 30 50 mv 6 hysteresis l -> h v slh(ha) hup,? 5 15 25 mv 7 hysteresis h -> l v shl(ha) hup,? -25 -15 -5 mv
electrical characteristcs L8150 10/37 table 9. torque optimizer input terminal t.o. no. item symbol terminal min typ max unit remark 1 max analog conversion input t.o. 15/25vreg 2 min analog conversion input t.o. 0 3 hysteresis t.o. 100 mv table 10. over current sense input terminal r no. item symbol terminal min typ max unit remark 1 over current sense level v rf rf 0.45 0.50 0.55 v table 11. forward backward select terminal fr (note 7 ) no. item symbol terminal min typ max unit remark 1 h level input voltage v ih (fr) fr 2.0 vreg v 2 l level input voltage v il (fr) fr 0.0 1.0 v 3 pull-up resistor to vreg r u (fr) fr -20% 50.0 +20% kohm 4 hysteresis width v is (fr) fr 0.2 0.3 0.4 v table 12. thermal sense input terminal tsd no. item symbol terminal min typ max unit remark 1 tsd threshold v ih (tsd) tsd 2.60 3.00 v 2hysteresis v hy (tsd) tsd 0.20 0.30 v table 13. fg output terminal fg no. item symbol terminal min typ max unit remark 1 output saturation voltage v fgl fg 0.50 v io=15ma, open drain 2 output leak current i fgleak fg 10 ua vo=16.5v table 14. osc terminal osc no. item symbol terminal min typ max unit remark 1 current setting v osc osc 1.235 v r=20.5kohm (class e96), fsys=512*fpwm 2 pwm frequency f pwm 18k 20.4k hz 17khz - 21khz for tj=0 to 125 deg table 15. op amp input output terminal in tin+, intin-, intout (note 3, note 4) no. item symbol terminal min typ max unit remark 1 h level output voltage v oh (int) intout 4.0 vreg2-0.2 vreg v io=1ma 2 l level output voltage v ol (int) intout 1.0 v io=1ma 3 input bias current i b (int) intin+, - -0.2 0.2 ua 4 offset v
L8150 electrical characteristcs 11/37 l note: 1 if 20ma is a problem for design because of power dissipation etc., it can be reduced to something like 5ma 2 one input is set at 2.5v by means of a resistor divider. the other input moves from 0v to vreg. the hall comparator must operate correctly for all its input range. 3 opamp need to be designed to meet with kval control by vsp. external circuit for vsp control (example) is shown in following figure 4 . the tolerance at vsp including external resistor (e96) is as follows: mini typ max v1(v) 0.85 1.23 1.6 v2(v) 1.7 2.1 2.5 v3(v) 4.9 5.4 6.1 4 fr and intin+ are used to set test mode as follows: test mode is set by 8 events (clock rising edges) on fr during intin+>4.5 (power is kept as high-impedance for intin+ > 4.5 until 7th event occur) (counter for fr is reset by intin+ < 4.5) table 16. over voltage protection terminal ov no. item symbol terminal min typ max unit remark 1 h level input voltage (operative) v ih (ov) ov -6% 3.0 +6% v 2 hysteresis width v is (ov) ov 0.3 0.4 v table 17. low voltage protection no. item symbol terminal min typ max unit remark 1 operation voltage v il (lv) lv 10 11 12 v 2 release voltage v ih (lv) lv 10.35 11.50 12.65 v 3 hysteresis width v is (lv) lv 0.35 0.50 0.65 v table 18. faults output terminal faults no. item symbol terminal min typ max unit remark 1 output saturation voltage v faultsl faults 0.50 v io=15ma, open drain 2 output leak current i faultsleak faults 10 ua vo=17.25v table 19. rotation directi on detection terminal dm no. item symbol terminal min typ max unit remark 1 output saturation voltage v dml dm 0.50 v io=15ma, open drain 2 output leak current i dmleak dm 10 ua vo=17.25v table 20. kval contro no. item symbol terminal min typ max unit remark 1 fs threshold voltage intout -3% 4.5vreg/5 +3% v note 3 2 kval min voltage intout -3% 3.7vreg/5 +3% v note 3 3 kval max voltage intout -7% 0.7vreg/5 +7% v note 3 4 fs hysteresis intout 70.0 mv
electrical characteristcs L8150 12/37 figure 3. kval control by vsp figure 4. external circuit for vsp control vsp 53.6k 46.4k 90.9k 22.1k 31. 6k vreg vo int amp network (suggested)
L8150 general description 13/37 4 general description 4.1 drive stage voltage-controlled pwm drive. smooth drive architecture (see following dedicated paragraph). external sense resistor as current limiter. fr terminal: low = forward, high or open = backward. 4.2 output u, v, w upper and lower arm power transistors control output (6 outputs) cmos level (low: 0v, high: 5v, need output buffer) dead time (0, 1usec, 1.5usec selectable). 4.3 i/o fg output: multiplexed by hall signal (open drain) (hall signal after digital filter are used) forward/backward control fault output: monitor signal for protection operation (low active, open drain), active if one of over voltage, lower voltage, thermal protection, hall sensor fail protection is operative torque optimizer: controlled by analog input dm output is the monitor signal of hall input sequence: ? if uvw hall signal sequence is as the direction set by fr, dm=h ? if uvw hall signal sequence is opposite for the direction set by fr, dm=l ? reset or some case in which uvw sequence can not be monitored, dm=h (hall signals after digital filter are used for this control). 4.4 hall sensor input terminals there are 2 types of application, hall device and hall ic hall device application: differential inputs with some bias hall ic application: one input is fixed around vreg/2 by resistor divider between vreg and gnd the other input comes from hall ic whose span is between 0 and 5v.
general description L8150 14/37 4.5 protection functions ? over-current protection: low side current recirculation for both smooth and rectangular drive in normal working condition. ? over-voltage protection: compare motor supply vdc (140v, 280v) and ic internal reference. all power transistor off (all 6 outputs = gnd) during over-voltage. return to normal operation if vdc is recovered from over-voltage condition. an hysteresis is present. lower voltage protection: all power tr off (all 6 outputs = gnd), if vcc is lower than a defined voltage threshold (all power transistors off if vcc is between 0 to the defined voltage threshold). return to normal operation if vcc is recovered from lower voltage condition. an hysteresis is present. thermal protection: all power transistors off by external thermal sense signal. if signal is high (exceeds vth), the power is off (all 6 output = gnd). hall sensor fail protection: all power transistor off (all output = gnd) if hall signals are hhh or lll (hall signals after digital filter are used). power on reset (sd): internal logic reset when power on or recovery from short time power off. all power transistor off (all 6 outputs = gnd) during reset. 4.6 pwm carrier frequency: 17-21khz for tj = 0 to 125 deg, 18khz - 20.4khz for tj = 25 c. 4.7 system clock internal oscillator: fsys =1/tck= 9.8 mhz typical value. one pin for external resistor sets the clock frequency (osc pin). 4.8 external hvic bootstrap capacitor initialization lower arm all on (3 outputs for low side are high, 3 outputs for high side are gnd) when vsp becoming on (free run releas e), (while this initializatio n should not be done when vsp becoming off) initializing time is 0.333 - 0.5 msec. 4.9 package 28 pins so28. it is suitable for both reflow and flow soldering. 4.10 others upper and lower arm pwm during rectangular drive; it means both side (upper and lower) chopping, not one side chopping, during rectangular drive).
L8150 general description 15/37 a maximum current of 5ma can be injected into ov protection terminal in case vcc = off and vdc = on without damaging the device. moreover the output does not cause malfunctioning (all power transistors are off). a maximum current of 5ma can be injected into to terminal from external circuit during vcc off without damaging the device. the output does not cause malfunctioning (all power transistors are off). a maximum current of 5ma can be injected into intinn termin al by vsp abnormal operation without damaging the device. the output does not cause malfunctioning (in particular it is needed to avoid vdc short-circuit by power transistor cross-conduction). osc pin sets the main bias currents for the whole device, including system clock.
operating description L8150 16/37 5 operating description 5.1 free-run (fs) and reset (sd) functions this device does not have an actual startup signal, the working or standby condition depends on two internally-generated signals: fs signal; sd (shut down) signal. the first one (fs) is related to the vsp external signal in the following way. given the transfer function of the intamp network shown below, which is obtained from the suggested intamp feedback network (see note 6 on electrical characteristics section): vo[v] = 5.617v - 0.909 vsp[v] we have that when vsp=1.23v, vo equals to 4. 5v; this signal (amplifier output) is fed to a comparator (fscomp) whose threshold is set at 4.5v (plus some hysteresis). when vo is greater than 4.5v the device is in the so called "free running" mode, that is all the power outputs are in high impedance; when the threshold is crossed the logic signal fs commutates from high to low, thus enabling normal device operation. the second one (sd) switches from high to low, thus enabling normal device operation. when sd is high it acts as a reset signal fo r the whole logic block and as a stand-by signal for the system oscillator and th e speed amplifier. sd = high is generated by a low voltage condition on vreg. 5.2 smooth drive and co ntrol logic description two basic driving techniques are applied according to different conditions: rectangular driving sinusoidal driving (smooth drive) the first one is used during startup phase or when the motor is rotating in the opposite direction with respect to fr signal or t>tmax, while smooth drive is used in normal operation. if a dc brushless motor has bemf voltage with a sinusoidal-like shape, also the currents in the windings are sinusoidal-like, if the applied voltage is sinusoidal. this means that the torque is almost constant and the ripple is very small, allowing acoustic noise reduction and lower emi. smooth drive basically applies three voltage patterns to the motor windings, each 120 electrical degrees out of phase with respect to the other, taking as reference the period measured during the last electrical period. in order to do this, an internal 16-bit counter (period counter) is provided which is triggered (current value is stored in a register and the counter is reset) at every rising edge of signal coming from u phase hall sensor (hallu). this kind of behavior is sketched in the picture ( figure 5 ), where the synchr onization control is represented by hallu rising edge. the clock of the counter is the system clock (fsys) divided by 36: this results in a maximum value of the electrical period that the device can measure and consequently a minimum speed at which smooth drive can work; this maximum period is: tmax = 36*38656*tck " 141.5 msec, with tck = 101.7ns (typical target value)
L8150 operating description 17/37 figure 5. 16 bit counter operation smooth drive basic functionality is to apply to the motor the voltage waveforms represented in the following pictures ( figure 6 ) in case of forward rotation (cw). figure 6. smooth drive pattern (forward) this kind of profile, which realizes waveforms t hat are differentially sinusoids, is digitally described by a table of 36 8-bit samples stored in a decoding circuit. the final amplitude of the voltage applied on the outputs is obtain ed by multiplying each sample by a value generated through an 8-bit adc, whose input is coming from the speed control. the motor is controlled in voltage mode, so no current control compensation network is required. actuation is done on motor windings through a fixed frequency pwm conversion. since smooth drive is basically a voltage mode driving there can be the need of shifting the applied profile with respect to the bemf (here sensed through the hall sensors). this applied phase shift is called torque optimizer . the value (expressed in electrical degrees, hereafter referred to as degrees) can be chosen applying an analog voltage to to pin, that will be internally converted using a 4-bit a/d. the phase shift range is from 2.5 to 40 degrees with a 2.5-degrees step. as a reference the correspondence between phase shift values and analog voltages is reported in ta bl e 2 1 .
operating description L8150 18/37 figure 7. phase shift vs input voltage the 4-bit a/d has an internal hysteresis so that "analog high thresholds" are the a/d thresholds applying a rising edge on to pin, the "analog low thresholds" are the a/d thresholds applying a falling edge on to pin. the applied phase shift "moves" the voltage profile with respect to the hall effect sensor in the direction indicated by the arrows in the picture. table 21. phase shift phase shift [c] analog low thresh old [v] analog high threshold [v] 2.5 <0.20 <0.30 5.0 0.20 0.30 7.5 0.40 0.50 10.0 0.60 0.70 12.5 0.80 0.89 15.0 0.99 1.09 17.5 1.19 1.29 20.0 1.39 1.49 22.5 1.59 1.68 25.0 1.78 1.88 27.5 1.98 2.08 30.0 2.17 2.27 32.5 2.37 2.47 35.0 2.57 2.66 37.5 2.76 2.86 40.0 2.96 3.05
L8150 operating description 19/37 in case of reverse rotation (ccw) , smooth drive applies the voltage profiles represented in the following pictures ( figure 8 ). figure 8. smooth drive pattern (reverse) in case sinusoidal mode cannot be applied, a rectan gular pattern will be applied, that is driving one phase fixed to gnd, one phase in tri-state while the other is switching from low to high with a duty cycle depending on the adc conversion , max. duty cycle about 95%, according to the following diagram: figure 9. rectangular drive pattern (forward) the diagram ( figure 9 ) is showing the applied driving patt ern in case of applied torque in forward (continuous blue line) dire ction, while in case of reverse (continuous red line) direction, the applied pattern can be found in the following picture ( figure 10 ); in both pictures the meaning of the pattern line is the following: when the line is low, the correspondent winding is driven continuously low; when the line is high, the winding is driven with a duty cycle defined from the adc co nversion at a frequency 512 times slower than the clock. on the other hand, when the line is at middle height the correspondent phase will be left tri-stated. hallu outu outv outw phase shift hallu hallu outu outv outw phase shift hallu hallv hallw outu outv outw hallu hallv hallw hallu hallv hallw outu outv outw hallu hallv hallw hallu hallv hallw outu outv outw hallu hallv hallw outu outv outw hallu hallv hallw hallu hallv hallw hallu hallv hallw outu outv outw
operating description L8150 20/37 figure 10. rectangular drive pattern (reverse) smooth drive mode is activated when three consecutive periods shorter than tmax are detected and device will keep driving in smooth mode until an external command is applied (through fr pin) or motor electrical period becomes longer than the maximum period the device is able to follow. startup phase (rectangular driving) is activa ted in one of the following conditions: when the period counter saturates; when the desired rotation direction (coming from fr command) is different from the detected rotation direction; sd = high low during all working conditions a current limitation circuit is active. it is composed of a current comparator sensing current flowing in the sense resistor (usually a sense resistor is connected between the sources of all power low side driver transistors and ground) and of some control logic. current limitation is achieved in three possible ways according to the different motor situations. the current limiter control method is a consequence of the rotation speed and the detected direction of the motor. let's divide the possible situations in two different cases: 1. the motor is rotating and its frequency is lower than the one used to switch between rectangular and sinusoidal driving pattern 2. the motor is rotating and its frequency is bigger than the one used to switch between rectangular and sinusoidal driving pattern in case 1) even if the detected rotation direction is different from the desired direction, the current limiter control method is to force two phases to gnd and one phase is left in high impedance state. in case 2) the possible situations can be the following: 2a) the desired direction is equal to the detected direction and sinusoidal mode is applied, the current limiter control method is forcing all the phases to gnd hallu hallv hallw outu outv outw hallu hallv hallw hallu hallv hallw outu outv outw
L8150 operating description 21/37 2b) the desired direction is not equal to the detected direction so that rectangular mode is used, the current limiter control method is forcing all the phases in high impedance state. in any case, current control method is updated every pwm cycle period. the amplitude of the voltage waveform applied to the motor windings allows the control to modulate the rotation speed; this is achieved through an 8-bit analog-to-digital converter (adc) transforming the output voltage of the control amplifier (intamp) into an 8-bit digital word that is used to scale the voltage waveform applied to the motor windings. a digital multiplier, whose inputs are the 8-bit samples of the voltage waveform (that is the output of the 8-bit adc), gives an 8-bit word that represents the voltage to be applied to the motor winding. furthermore, control signal actuation is pe rformed through a fixed frequency digital pwm converter, that is converting the 8-bit word co ming from the comparator into a digital signal, whose duty cycle is proportional to the result ing voltage to be applied to the motor windings. the period of the pwm output signal is: t pwm = 512 tck resulting in a frequency that is 19.2 khz in the typical case. motor position is detected through a set of th ree hall sensor, whose output is differentially fed into the device; after processing the signal by means of a comparator (whose characteristics are explained in the electrical characteristics section) the signal is furtherly filtered through a digital circuit to prevent noise from causing any device malfunctioning. the filtering circuit processes signals coming from hall sensors comparators (hallu, hallv, hallw) and generates a set of three internal sign als used inside the digital part of the circuit (posfil). figure 11. filtering circuit in order to simplify the explanat ion of the filtering circuit a si gnal pos will be defined that can assume 7 different values according to the following table: the filtering action takes place according to the following picture (fig. 7). table 22. 7 different values of the signal pos hallu 1110000 hallv 0011100 hallw 1000110 posp1p2p3p4p5p6perr hallu hallv hallw posfil hall sensor filtering block from input comparator to control logic 3
operating description L8150 22/37 figure 12. filter block diagram the filter working principle is explained in the previous diagram ( figure 12 ): the main component of the filter circuit is a 12-bit counter that is reset (to the value 0) whenever the posfil signal is equal to the pos one. when the two signals are different (meaning that a transition is happening), the counter will start counting as long as one of the following conditions will occur: pos signal is again equal to former posfil : in this case a noise is generating some hall comparator commutation, the counter has reached or overcome the value set by filter length signal: in this case the internal hall signals will be latched into the posfil register; immediately after this event, posfil will become equal to pos and the counter will be reset. at the same time (at the end of the filtering time), a flip-flop detecting the direction is updated with the right direction information according to the former hall decoding posfil and the new one pos, immediately before latching it into the register. 12-bit filter length is set to two values according to different possibilities: maximum filtering time, corresponding to 4096 clock periods ( 420us in the typical case, same used for pre-charge function) when an hall effect commutation is detected just after a startup signal edge (sd or fs) and before tmax/6 is elapsed. this filtering time is also used when the motor accelerate starting from a stopped condition (no hall effect commutation is detected from fs or sd edge to tmax/6) the filter length is a fraction of the elapsed time between two zero crossing signal (zc). during normal working (in case motor period is shorter than tmax) it is equivalent to 0.625 electrical degrees. a zc signal is produced every time one of these situations happens: a falling edge of the fs signal is detected a rising edge of the hallu signal is detected any hall effect commutations when the high impedance condition is forced by the ic and the motor is in free-run condition >= 1 = 12 bit counter pos fil register ck pos posfil posfil latch enable filter length reset 3 12 12 delay 1 tclk >= 1 = 12 bit counter pos fil register ck pos posfil posfil latch enable filter length reset 3 12 12 delay 1 tclk
L8150 operating description 23/37 5.3 speed control circuitry the rotation speed control sign al (vsp) is an external signal, whose range is 2.1v 5.4v. this signal is amplified by an inverting amplifier which takes as reference a voltage derived from vreg through a voltage divider. the amplifier output is the input signal of an 8-bit adc which generates the digital word kval, used to determine the duty cycle value according to the following figure 13 : speed control: intout 0-0.7v: duty =100% for smooth drive (max duty is limited at about 95% for re ctangular as shown in the following figure) intout 0.7-3.7v: duty control 100-0% intout 3.7-4.5: duty = 0 % intout 4.5v - 5v (vreg): all power off (all 6 output = gnd) (each vth depends linearly on vreg, being obtained by means of voltage dividers). figure 13. duty cycle
precharge and hall effects filtering time description L8150 24/37 6 precharge and hall effects filtering time description 6.1 startup sequence with fs signal let?s startup sequence forced by fs comparator, assuming the motor is not rotating: figure 14. startup sequence forced by fs comparator, assuming the motor is not rotating when the signal coming from the fs comparator has a falling edge (corresponding to a vsp signal crossing the 1.23v threshold), the logic starts counting, to verify if the motor is rotating or not. if the motor is stopped and no hall effect commutation is detected, the counter has reached its saturation time, given by the following equation: n.b . telmax is equal to tmax used in the previous sections of this document. after this saturation time the logic has decide d to do a precharge function, and for a period of time given by the following equation all the output logic signals ul,vl,wl become high while the signals uh, vh, wh are low. when the precharge is over, the logic outputs start applying the right rectangular pattern to accelerate the motor. during this sequence the hall f iltering time is 400usec until the first rising edge on signal hallu is detected. then a filter given by the following equation is used: t ? zc is the elapsed time between two consecutive zero-crossing signals. by default a zero- crossing signal is generated when a falling edge of the fs comparator is detected, and after that a zero-crossing signal is generated when a rising edge on signal hallu is detected. fs precharge zc hall bus filter time phases phases excited 400 us 400 us 400 us t ? zc/576 t ? zc tel u telmax/6 motor accelerating 400 us 400 us tel max 7mhz () 1 ? 141.5msec tel max 6 -------------------- - 24msec ? ? ? = t charge 4096 t ck 400 sec ? ? = t filter 1 576 --------- - t ? zc ? =
L8150 precharge and hall effects filtering time description 25/37 assumed this operation mode, it is easy to un derstand that as soon as the startup sequence is over, hall effects commutations are filtered us ing a fraction of the electrical period given by the following equation, since t ? zc is equal to tel when two consecutive zero-crossing signals generated by a rising edge on signal hallu are detected: let's consider a startup sequence forced by fs comparator, supposing the motor rotating quickly in the direction imposed by the fr signal: figure 15. startup sequence forced by fs comparator, supposing the motor rotating quickly in the direction imposed by the fr signal: when the signal coming from the fs comparator has a falling edge, by default a zero- crossing signal is generated and the logic waits for a hall effect commutation and applies to it a filtering time of t precharge =400 sec. the first significant zero-crossing signal is generated. also the second hall effect commutation is filtered using t precharge , after that the second zero-crossing signal is generated. starting from the second hall effect commutation, after the acquisition of the filtered hall commutation, the logic outputs start applying the right pattern, and the motor is able to accelerate again. the next filtering time used for the hall commutation is a fraction of the elapsed time between the first two hall effect commutations, according to the previous t filter equation. this filtering time is used unt il the first rising edge on sign al hallu is detected and a zero- crossing signal is generated. after that the f iltering time used is a fraction of the elapsed time between the last two detected zero-crossing signals, in other words between the second hall effect commutation and the rising edge on signal hallu. finally, when the second rising edge on signal ha llu is detected, the filtering time used is a fraction of the electrical period, as described in previous t filter-rotating equation. let's consider a startup sequence forced by fs comparator, supposing the motor rotating quickly in the direction opposite to that imposed by the fr signal: t filter roating ? 1 576 --------- - t ? zc 1 576 --------- - t el ? = ? = fs zc hall bus filter time phases phases excited t ? zc??/576 t ? zc? tel u motor accelerating 400 us t ? zc?? t ? zc?/576 t ? zc?/576 t ? zc?/576 t ? zc??/576 400 us
precharge and hall effects filtering time description L8150 26/37 figure 16. startup sequence forced by fs comparator, supposing the motor rotating quickly in the direction opposite to that imposed by the fr signal this situation is similar to the one described before, except dm behaviour. let's suppose the fs signal high, which means all phases in high impedance state. even if the signal fs is high, the logic is able to detect if the motor is rotating in the desired direction or not. so when the signal coming from the fs compar ator has a falling edge, by default a zero- crossing signal is generated and the dm signal is already low, indicating that the detected direction is not equal to desired direction. from now on the logic waits for a hall effect comm utation and applies to it a filtering time of t precharge =400 sec. the first significant zero-crossing signal is generated. also the second hall effect co mmutation is filtered using t precharge , and the second zero- crossing signal is generated. starting form the second hall effect commutation, after the acquisition of the filtered hall commutation, the logic outputs start applying the rectangular pattern, and the motor is able to decelerate until the rotation direction changes becoming equal to the desired one. after the first two hall commutations, the filtering time used is a fraction of the elapsed time between the first two hall effect commutations, according to the previous t filter equation. this filtering time is used unt il the first rising edge on sign al hallu is detected and a zero- crossing signal is generated. after that the f iltering time used is a fraction of the elapsed time between the last two detected zero-crossing signals, in other words between the second hall effect commutation and the rising edge on signal hallu. finally, when the second rising edge on signal ha llu is detected, the filtering time used is a fraction of the electrical period, as described in previous t filter-rotating equation. only when a hall effect commutation consistent with the desired direction is detected the dm signal becomes high, indicating the right direction detection. let's consider a startup sequence forced by fs comparator, supposing the motor rotating too quickly: fs zc hall bus filter time phases phases excited t ? zc? motor decelerating 400 us 400 us t ? zc?/576 t ? zc?/576 motor accelerating dm t ? zc?/576 t ? zc?/576
L8150 precharge and hall effects filtering time description 27/37 figure 17. startup sequence forced by fs comparator, supposing the motor rotating too quickly when the signal coming from the fs comparator has a falling edge, by default a zero- crossing signal is generated and the logic waits for a hall effect commutation and applies to it a filtering time of t precharge = 400 sec. if the motor is rotating too quickly the next hall effect commutation happens before the filtering ti me is elapsed: this causes the reset of the filter and, in consequence, a new count for the filter time of 400 sec. until the motor is rotating too quickly no hall effect commutation is acquired by the logic, thus the logic outputs force high impedance condition. only when the motor speed becomes lower than the speed necessary to obtain a tel/6>400 sec the hall effect commutations are filtered and acquired. if no hall effect commutation is acquired during a period of telmax/6, a precharge function will be done. depending on the last filtered hall effect codification present in the logic and, also, on the hall effect codification having a duration longer than 400 sec (because the hall effect codifications filtered have to be consecutive), the hall effect commutations filtered using a filter time of 400usec could be two or, more probably, three. after this hall effect commutations the logic outputs start applying the right pattern to the motor windings. the motor rotation direction is irrelevant, in fact this can influence only the kind of pattern applied after the two or three filtered hall effect commutation. let's consider a startup sequence forced by fs-comparator, supposing the motor rotating slowly. when the signal coming from the fs comparator ha s a falling edge, the logic waits for a hall effect commutation for a period of time equal to telmax/6. if no hall effect commutation happens during this time, the behaviour is the one described in the previous section, when a startup sequence with motor stopped is described. let's suppose that during the counting period of telmax/6 a hall effect commutation is detected. this commutation is filtered using 400usec. considering the hypothesis done, starting from the hall effect commutation detection , no more commutation will be detected fs zc hall bus filter time phases phases excited t ? zc??/576 t ? zc? tel u motor rotating too fast 400 us t ? zc?? 400 us t ? zc?/576 t ? zc? 400 us
precharge and hall effects filtering time description L8150 28/37 for the successive telmax/6 and the behaviour is the one described in the startup sequence with motor stopped. 6.2 startup sequence with sd signal let's consider a startup sequence forced by sd, supposing the motor stopped: figure 18. startup sequence forced by sd, supposing the motor stopped when the sd signal has a fallin g edge (corresponding to a vreg signal that's crossing the lower voltage protection), the logic can prod uce a zc signal, depending on fs signal behaviour induced by vsp voltage value. in any case, even if no zc signal is produced, if the motor is stopped and no hall effect commutation is detected, the counter reaches its saturation time telmax/6 and the system evolves like in the situation described in previous startup sequence with motor stopped. let's consider a startup sequence forced by sd, supposing the motor rotating quickly in the direction imposed by the fr signal: figure 19. startup sequence forced by sd, supposing the motor rotating quickly in the direction imposed by the fr signal sd precharge zc hall bus filter time phases phases excited 400 us 400 us 400 us t ? zc/576 t ? zc tel u telmax/6 motor accelerating 400 us 400 us sd zc hall bus filter time phases phases excited t ? zc/576 tel 400 us t ? zc/576 t ? zc/576 t ? zc/576 t ? zc 400 us
L8150 precharge and hall effects filtering time description 29/37 when the sd signal has a fallin g edge the logic acquires the hall codification and waits for next hall effect commutation, which is filtered using a filtering time of t precharge = 400 sec. the first significant zero-crossing signal is generated. also the second hall effect commutation is filtered using t precharge , after that the second zero-crossing signal is generated. starting form the second hall effect commutation, after the acquisition of the filtered hall commutation, the logic outputs start applying the right pattern, and the motor is able to accelerate again. next filtering time used for the hall commutation is a fraction of the elapsed time between the last two zero-crossing signals tdzc. this filtering time is used until the first rising edge on signal hallu is detected and a new zero-crossing signal is generated. let's consider a startup sequence forced by sd, supposing the motor rotating quickly in the direction not imposed by the fr signal: figure 20. startup sequence forced by sd, supposing the motor rotating quickly in the direction not imposed by the fr signal this situation is similar to th at described before, except dm behaviour. let's suppose the sd signal high, which means all phases in high im pedance state. since the signal sd is high and considering that this is the reset signal for the whole logic part, the system is not able to detect if the mo tor is rotating in the desired directio n or not and by default the dm signal will be high. so when the signal sd has a falling edge, the dm signal remains high, indicating that the detected direction is equal to desired direction. only after the first filtered hall effect commutation the system is able to determines if the rotation direction is equal to the desired one. at this moment the dm signal becomes low. starting from the second hall effect commutation, after the acquisition of the filtered hall commutation, the logic outputs starts applying the right pattern, and the motor starts to decelerate. sd zc hall bus filter time phases phases excited t ? zc motor decelerating 400 us 400 us t ? zc/576 motor accelerating dm t ? zc/576 t ? zc/576 t ? zc/576 motor free run
precharge and hall effects filtering time description L8150 30/37 only when an hall effect commutation consistent with the desired direction is detected, the dm signal becomes high, indicating the right direction detection. let's consider a startup sequence forced by sd signal, supposing the motor rotating too quickly: figure 21. startup sequence forced by sd signal, supposing the motor rotating too quickly when the sd signal has a fallin g edge the logic waits for an hall effect commutation. if the motor is rotating too quickly the next hall effect commutation occurs before the filtering time has elapsed. this means that a new hall filter count is performed and no hall effect codification is acquired until t precharge has elapsed while the hall bus is not changed. until the motor rotates too quickl y no hall effect commutation is acquired by the logic, thus the logic outputs force high impedance condition. only when the motor speed becomes lower than the speed necessary to obtain a tel/6>400 sec the hall effect commutation are filtered and acquired. after the first two or three filtered hall effect commutations (because they have to be consecutive), the logic outputs start applying the right pattern to the motor windings. the motor rotation direction is not important, in fact this can influence only the kind of pattern applied after the two or three filtered hall effect commutation. in the picture is reported the less likely situation. let's consider a startup sequence forced by sd, supposing the motor rotating slowly. when the signal coming from the sd-comparator has a falling edge, the logic waits for an hall effect commutation for a period of time equal to telmax/6. if no hall effect commutation occurs during this time, the behaviour is that described in the previous section, when a startup sequence with motor stopped is described. let's suppose that during the counting period of telmax/6 an hall effect commutation is detected. this commutation is filtered using 400 sec. considering the hypothesis done, starting from the hall effect commutation detection , no more commutation will be detected for the following telmax/6 and the behaviour is the one described in the startup sequence with motor stopped. sd zc hall bus filter time phases phases excited t ? zc??/576 t ? zc? tel u motor rotating too fast t ? zc?? 400 us t ? zc?/576 400 us
L8150 application example 31/37 7 application example figure 22. basic motor control circuit
application example L8150 32/37 figure 23. 3 phases motor control circuit
L8150 input output pins interface 33/37 8 input output pins interface in the following the simplified sche matics of all the device pins. figure 24. pins: tsd, ov, sdt, intinn, intinp figure 25. pins: to figure 26. pins: rf figure 27. pins: intout figure 28. pins: osc figure 29. pins: fg, dm, fault vreg tsd,ov,sdt, intinn,intinp d01in1267 vreg always off to d01in1268 vreg rf d01in1269 vreg intout active during adcs sampling d01in1270 vreg osc d01in1271 vreg fg,dm fault d01in1272
input output pins interface L8150 34/37 figure 30. esd clamping fi gure 31. recirculation diode figure 32. pins: fr figure 33. pins: hwn, hwp figure 34. pins: hun, huvp, hvn, hvp f igure 35. pins: uh, ul, vh, vl, wh, wl esd clamp d01in1273 device vcc gnd d01in1274 device vreg gnd vreg on in test mode fr d01in1275 vreg hwn,hwp d01in1276 vreg on in test mode hun,hup hvn,hvp d01in1277 vreg uh,ul vh,vl wh,wl on during power up d01in1278
L8150 package information 35/37 9 package information in order to meet environmental requirements, st offers these devices in ecopack? packages. these packages have a lead-free second level interconnect. the category of second level interconnect is marked on the package and on the inner box label, in compliance with jedec standard jesd97. the maximum ratings related to soldering conditions are also marked on the inner box label. ecopack is an st trademark. ecopack specifications are available at: http://www.st.com. figure 36. so-28 mechanical data & package dimensions so-28 dim. mm inch min. typ. max. min. typ. max. a 2.65 0.104 a1 0.1 0.3 0.004 0.012 b 0.35 0.49 0.014 0.019 b1 0.23 0.32 0.009 0.013 c 0.5 0.020 c1 45 (typ.) d 17.7 18.1 0.697 0.713 e 10 10.65 0.394 0.419 e 1.27 0.050 e3 16.51 0.65 f 7.4 7.6 0.291 0.299 l 0.4 1.27 0.016 0.050 s8 (max.) outline and mechanical data
revision history L8150 36/37 10 revision history table 23. document revision history date revision changes 20-mar-2006 1 initial release.
L8150 37/37 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a parti cular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. unless expressly approved in writing by an authorize representative of st, st products are not designed, authorized or warranted for use in military, air craft, space, life saving, or life sustaining applications, nor in products or systems, where failure or malfunction may result in personal injury, death, or severe property or environmental damage. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or registered trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2006 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

▲Up To Search▲

Price & Availability of L8150

	To Download L8150 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .